Semiconductor die package with thermal management features and method for forming the same

ABSTRACT

A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, and a first semiconductor die and a second semiconductor die disposed thereon. A ring structure is attached to the package substrate and surrounds the semiconductor dies. A lid structure is attached to the ring structure and disposed over the semiconductor dies, and has an opening exposing the second semiconductor die. A heat sink is disposed over the lid structure and has a portion extending into the opening of the lid structure. A first thermal interface material (TIM) layer is interposed between the lid structure and the first semiconductor die. A second TIM layer is interposed between the extending portion of the heat sink and the second semiconductor die. The first TIM layer has a thermal conductivity higher than the thermal conductivity of the second TIM layer.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment. Semiconductor devices are fabricated bysequentially depositing insulating or dielectric layers, conductivelayers, and semiconductor layers over a semiconductor substrate, andpatterning the various material layers using lithography and etchingprocesses to form circuit components and elements thereon. Manyintegrated circuits (ICs) are typically manufactured on a singlesemiconductor wafer, and individual dies on the wafer are singulated bysawing between the integrated circuits along a scribe line. Theindividual dies are typically packaged separately, in multi-chipmodules, for example, or in other types of packaging.

A package not only provides protection for semiconductor devices fromenvironmental contaminants, but also provides a connection interface forthe semiconductor devices packaged therein. One smaller type ofpackaging for semiconductors is a flip chip chip-scale package (FcCSP),in which a semiconductor die is placed upside-down on a substrate andbonded to the substrate using bumps. The substrate has wiring routed toconnect the bumps on the die to contact pads on the substrate that havea larger footprint. An array of solder balls is formed on the oppositeside of the substrate and is used to electrically connect the packageddie to an end application.

Although existing packaging structures and methods for fabricatingsemiconductor die package structure have generally been adequate fortheir intended purposes, they have not been entirely satisfactory in allrespects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1H are schematic cross-sectional views of various stages of aprocess for forming a semiconductor die package in accordance with someembodiments.

FIG. 1F-1 is a schematic cross-sectional view of a stage of a processfor forming a semiconductor die package in accordance with some otherembodiments, wherein the TIM layer 140 is only provided on the firstsemiconductor die 110 and is a continuous structure without openingsformed therein.

FIG. 1F-2 is a schematic cross-sectional view of a stage of a processfor forming a semiconductor die package in accordance with some otherembodiments, wherein the lid structure 150 and the ring structure 130are one-piece, and such one-piece structure is attached to the packagesubstrate 120 in a single step using the adhesive layer 132.

FIG. 1H-1 is a schematic cross-sectional view of a semiconductor diepackage in accordance with some other embodiments, wherein the thicknessof TIM layer 180 is less than the thickness of TIM layer 140.

FIG. 2 is a schematic top view of a portion of a semiconductor diepackage in accordance with some embodiments, wherein the lid structureand the heat sink are not shown.

FIG. 3A is a cross-sectional view view of a portion of a semiconductordie package in accordance with some embodiments.

FIG. 3B is an exploded view of a portion of a semiconductor die packagein accordance with some embodiments

FIG. 4 is a closed-up cross-sectional view of a thermal stack inaccordance with some embodiments.

FIG. 5A is a cross-sectional view of a portion of a semiconductor diepackage in accordance with some other embodiments.

FIG. 5B is an exploded view of a portion of a semiconductor die packagein accordance with some other embodiments

FIG. 6A is a schematic cross-sectional view of a portion of asemiconductor die package in accordance with some other embodiments.

FIG. 6B is a schematic cross-sectional view of a portion of asemiconductor die package in accordance with some other embodiments

FIG. 7 is a simplified flowchart illustrating a method for forming asemiconductor die package in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The term “substantially” in the description, such as in “substantiallyflat” or in “substantially coplanar”, etc., will be understood by theperson skilled in the art. In some embodiments the adjectivesubstantially may be removed. Where applicable, the term “substantially”may also include embodiments with “entirely”, “completely”, “all”, etc.Where applicable, the term “substantially” may also relate to 90% orhigher, such as 95% or higher, especially 99% or higher, including 100%.Furthermore, terms such as “substantially parallel” or “substantiallyperpendicular” are to be interpreted as not to exclude insignificantdeviation from the specified arrangement and may include for exampledeviations of up to 10°. The word “substantially” does not exclude“completely” e.g. a composition which is “substantially free” from Y maybe completely free from Y.

Terms such as “about” in conjunction with a specific distance or sizeare to be interpreted so as not to exclude insignificant deviation fromthe specified distance or size and may include for example deviations ofup to 10%. The term “about” in relation to a numerical value x may meanx±5 or 10%.

A semiconductor die package and the method for forming the same areprovided in accordance with various embodiments. Some variations of someembodiments are discussed. Throughout the various views and illustrativeembodiments, like reference numbers are used to designate like elements.

In accordance with some embodiments of the present disclosure, asemiconductor die package includes a heat sink disposed above a lidstructure to dissipate heat. The lid structure is attached to ahigh-power consuming die in the semiconductor die package through afirst thermal interface material (TIM) layer. The heat sink has aprotrusion that passes through an opening of the lid structure and isattached to a low-power consuming die in the semiconductor die packagethrough a second TIM layer. The heat transfer of the low-power consumingdie can be improved by the heat sink protrusion and the second TIMlayer, which will be further described later. In some embodiments, thefirst TIM layer utilizes metallic-based or solder-based TIM, and thesecond TIM layer utilizes polymer TIM instead of metallic-based orsolder-based TIM. Therefore, there is no need to perform an additionalbackside metallization (BSM) process on the backside of the low-powerconsuming die to facilitate bonding with the second TIM layer (polymerTIM), so costs can be reduced. Further, since polymer TIM has a goodadhering ability, the risk of delamination of the second TIM layer canalso be reduced, thereby improving the reliability of the entire packagestructure.

Embodiments will be described with respect to a specific context, namelya packaging technique with an interposer substrate or other active chipin a two and a half dimensional integrated circuit (2.5DIC) structure ora three dimensional IC (3DIC) structure. Embodiments discussed hereinare to provide examples to enable making or using the subject matter ofthis disclosure, and a person having ordinary skill in the art willreadily understand modifications that can be made while remaining withincontemplated scopes of different embodiments. Although methodembodiments may be discussed below as being performed in a particularorder, other method embodiments contemplate steps that are performed inany logical order.

FIGS. 1A-1H are schematic cross-sectional views of various stages of aprocess for forming a semiconductor die package in accordance with someembodiments. As shown in FIG. 1A, an interposer substrate 102 is formedover a carrier substrate 100, in accordance with some embodiments. Thecarrier substrate 100 is used to provide temporary mechanical andstructural support for the processing of build-up layers or structuresduring subsequent processing steps. The carrier substrate 100 may be aglass substrate, semiconductor substrate, or another suitable substrate.The interposer substrate 102 is used to provide electrical connectionbetween semiconductor devices or components packaged thereon and apackage substrate (which will be described later), after the carriersubstrate 100 is removed at a subsequent stage illustrated in FIG. 1C.

In some embodiments, the interposer substrate 102 is an interposerwafer, which is free from active devices (such as transistors anddiodes) and passive devices (such as resistors, capacitors, inductors,or the like). In some alternative embodiments, the interposer substrate102 is a device wafer including active and/or passive devices thereon ortherein.

In some embodiments, the interposer substrate 102 is a dielectricsubstrate, which includes a redistribution line (RDL) structure. Asshown in FIG. 1A, the RDL structure includes multiple laminatedinsulating layers 104 and multiple conductive features 106 surrounded bythe insulating layers 104. The conductive features 106 may includeconductive lines, conductive vias, and/or conductive pads. In someembodiments, some of the conductive vias are stacked with each other.The upper conductive via is substantially aligned with the lowerconductive via so as to have a shorter routing length. However, some ofthe conductive vias may be staggered vias in some cases with restrictedrouting. The upper conductive via is misaligned with the lowerconductive via.

The insulating layers 104 may be made of or include one or more polymermaterials. The polymer material(s) may include polybenzoxazole (PBO),polyimide (PI), epoxy-based resin, one or more other suitable polymermaterials, or a combination thereof. In some embodiments, the polymermaterial is photosensitive. A photolithography process may therefore beused to form openings with desired patterns in the insulating layers104.

In some other embodiments, some or all of the insulating layers 104 aremade of or include dielectric materials other than polymer materials.The dielectric material may include silicon oxide, silicon carbide,silicon nitride, silicon oxynitride, one or more other suitablematerials, or a combination thereof.

The conductive features 106 may include conductive lines providingelectrical connection in horizontal directions and conductive viasproviding electrical connection in vertical directions. The conductivefeatures 106 may be made of or include copper, aluminum, gold, cobalt,titanium, nickel, silver, graphene, one or more other suitableconductive materials, or a combination thereof. In some embodiments, theconductive features 106 include multiple sub-layers. For example, eachof the conductive features 106 contains multiple sub-layers includingTi/Cu, Ti/Ni/Cu, Ti/Cu/Ti, Al/Ti/Ni/Ag, other suitable sub-layers, or acombination thereof.

The formation of the above RDL structure (i.e., interposer substrate102) may involve multiple deposition or coating processes, multiplepatterning processes, and/or multiple planarization processes.

The deposition or coating processes may be used to form insulatinglayers and/or conductive layers. The deposition or coating processes mayinclude a spin coating process, an electroplating process, anelectroless process, a chemical vapor deposition (CVD) process, aphysical vapor deposition (PVD) process, an atomic layer deposition(ALD) process, one or more other applicable processes, or a combinationthereof.

The patterning processes may be used to pattern the formed insulatinglayers and/or the formed conductive layers. The patterning processes mayinclude a photolithography process, an energy beam drilling process(such as a laser beam drilling process, an ion beam drilling process, oran electron beam drilling process), an etching process, a mechanicaldrilling process, one or more other applicable processes, or acombination thereof.

The planarization processes may be used to provide the formed insulatinglayers and/or the formed conductive layers with planar top surfaces tofacilitate subsequent processes. The planarization processes may includea mechanical grinding process, a chemical mechanical polishing (CMP)process, one or more other applicable processes, or a combinationthereof.

In some alternative embodiments (not shown), the interposer substrate102 may be a semiconductor substrate, which may be a bulk semiconductorsubstrate, a silicon-on-insulator (SOI) substrate, a multi-layeredsemiconductor substrate, or the like. The semiconductor material of theinterposer substrate 102 may be silicon, germanium, a compoundsemiconductor including silicon germanium, silicon carbide, galliumarsenic, gallium phosphide, indium phosphide, indium arsenide, and/orindium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs,AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Othersubstrates, such as multi-layered or gradient substrates, may also beused. The interposer substrate 102 may be doped or undoped.

In some embodiments, through-vias (TVs) are formed in and penetratingthrough the semiconductor substrate, in order to provide electricalconnection between devices mounted on opposite sides of the interposersubstrate 102. The processes for forming the through-vias are well knownin the art and therefore not described herein. In some furtherembodiments, one or more interconnect structure layers (similar to theRDL structure of interposer substrate 102 shown in FIG. 1A) may beformed on one or both sides of the semiconductor substrate of interposersubstrate 102 for routing.

As shown in FIG. 1B, semiconductor dies 110 and semiconductor dies 112(for illustration, only one semiconductor die 110 and two semiconductordies 112 are shown) are disposed over the interposer substrate 102, inaccordance with some embodiments. The semiconductor dies 110 and 112 maybe placed over a first surface 102A (e.g., the upper surface shown inFIG. 1B) of the interposer substrate 102 using, for example, apick-and-place tool. In some embodiments, in the top view of a packagestructure, one semiconductor die 110 is disposed between twosemiconductor dies 112, as shown in FIG. 2.

FIG. 2 is a top view of a portion of a package structure in accordancewith some embodiments, showing the arrangement of the semiconductor dies110 and 112 (for example, multiple semiconductor dies 112 are arrangedon opposite sides of the semiconductor die 110). However, the disclosureis not limited to the embodiments shown in FIG. 2, and otherconfigurations and any number of semiconductor dies 110 and 112 can beused in different embodiments. The semiconductor dies 110 and 112 areeach generally rectangular or square in the top view, but the disclosureis not limited thereto.

In some embodiments, the semiconductor dies 110 (also referred to asfirst semiconductor dies 110 herein) and the semiconductor dies 112(also referred to as second semiconductor dies 112 herein) are differenttypes of electronic devices that provide different functions. In someembodiments, the first semiconductor die 110 is a high-power consumingdie and may consume a relatively high amount of power, and thereforegenerate a relatively large amount of heat, compared to the secondsemiconductor die 112 (thus also referred to as a low-power consumingdie). For example, the first semiconductor die 110 may consume betweenabout 50 W and about 100 W of power, whereas the second semiconductordie 112 may consume between about 5 W and about 10 W of power.

In some embodiments, the first semiconductor die 110 may be a singleSystem on a Chip (SoC) die, multiple SoC stacked dies, or the like. Forexample, FIG. 1B illustrates that the first semiconductor die 110 is aSoC die, which includes a semiconductor substrate 1101, and multipledifferent electronic components 1102 (such as active components and/orpassive components) mounted on the semiconductor substrate 1101. Theelectronic components 1102 may be electrically connected through thesemiconductor substrate 1101 to form a functional integrated circuit,such as a processor, logic circuitry, memory, analog circuit, digitalcircuit, mixed signal circuit, or the like. A protective layer 1103 madeof molding material (such as an epoxy-based resin) may be disposed onthe semiconductor substrate 1101 to surround and protect the overlyingelectronic components 1102, in accordance with some embodiments.

In some embodiments, the second semiconductor die 112 may be a singlememory die or a memory die stack. For example, FIG. 1B illustrates thatthe second semiconductor die 112 is a memory die stack, which includesmultiple stacked memory dies 1122 bonded to a logic die 1121 (sometimescalled a base die). Each of the memory dies 1122 may include a staticrandom access memory (SRAM) device, a dynamic random access memory(DRAM) device, a high bandwidth memory (HBM) device, or another type ofmemory device. A protective layer 1123 made of molding material (such asan epoxy-based resin) may also be formed to surround and protect thelogic die 1121 and the memory dies 1122, in accordance with someembodiments.

Each of the semiconductor dies 110 and 112 can be obtained, for example,by sawing or dicing a semiconductor wafer (with several IC dies formedthereon) along scribed lines to separate the semiconductor wafer into aplurality of individual semiconductor dies. It should be appreciatedthat the above examples of semiconductor dies 110 and 112 are providedfor illustrative purposes, and other semiconductor dies or chips havingother functions may also be used in some alternative embodiments.

In various embodiments, the semiconductor dies 110 and 112 may have thesame or different heights in a vertical direction (e.g., the direction Zshown in FIG. 1B), and/or the same or different sizes in a horizontalcross section perpendicular to the vertical direction.

After disposing the semiconductor dies 110 and 112 over the interposersubstrate 102, they are bonded to the interposer substrate 102 throughflip-chip bonding by way of conductive elements 107 on eachsemiconductor die 110/112 and conductive structures 108 on theinterposer substrate 102 to form conductive joints, as shown in FIG. 1B,in accordance with some embodiments.

In some embodiments, the conductive elements 107, such as conductivepillars, may be formed on an active side (e.g., the lower surface shownin FIG. 1B) of each semiconductor die 110/112 at the exposed contactpads (not shown) before the bonding process. The conductive elements 107may be made of or include copper, aluminum, gold, cobalt, titanium, tin,one or more other suitable materials, or a combination thereof. Theconductive elements 107 may be formed using an electroplating process,an electroless plating process, a placement process, a printing process,a physical vapor deposition (PVD) process, a chemical vapor deposition(CVD) process, one or more other applicable processes, or a combinationthereof.

In some embodiments, each of the conductive structures 108 includes ametal pillar 108A and a metal cap layer (such as a solder cap) 108B overthe metal pillar 108A, as shown in FIG. 1B. The conductive structures108 including the metal pillars 108A and the metal cap layers 108B aresometimes referred to as micro bumps. The conductive structures 108 maybe formed on the first surface 102A of the interposer substrate 102 atthe exposed contact pads (not shown) before the bonding process.

The metal pillars 108A may include a conductive material such as copper,aluminum, gold, nickel, palladium, the like, or a combination thereof,and may be formed by sputtering, printing, electroplating, electrolessplating, CVD, or the like. The metal pillars 108A may be solder-free andhave substantially vertical sidewalls. In accordance with someembodiments, a metal cap layer 108B is formed on the top of a metalpillar 108A. The metal cap layers 108B may include nickel, tin,tin-lead, gold, copper, silver, palladium, indium,nickel-palladium-gold, nickel-gold, the like, or a combination thereof,and may be formed by a plating process such as an electroplatingprocess. One of ordinary skill in the art would appreciate that theabove conductive structures 108 examples are provided for illustrativepurposes, and other structures of the conductive structures 108 may alsobe used.

The bonding between the semiconductor dies 110 and 112 and theinterposer substrate 102 may be solder bonding or direct metal-to-metal(such as a copper-to-copper) bonding, in accordance with someembodiments. In some embodiments, the semiconductor dies 110 and 112 arebonded to the interposer substrate 102 through a reflow process. Duringthe reflow, the conductive joints (i.e., the conductive elements 107 andthe conductive structures 108) are in contact with the exposed contactpads of the semiconductor dies 110 and 112 and the exposed contact pads(constructed by some conductive features 106) of the interposersubstrate 102, respectively, to physically and electrically couple thesemiconductor dies 110 and 112 to the interposer substrate 102.

In some embodiments, an underfill element 114 is further formed over theinterposer substrate 102 to surround and protect the conductive joints,and enhances the connection between the semiconductor dies 110 and 112and the interposer substrate 102, as shown in FIG. 1B. The underfillelement 114 may be made of or include an insulating material such as anunderfill material. The underfill material may include an epoxy, aresin, a filler material, a stress release agent (SRA), an adhesionpromoter, another suitable material, or a combination thereof. In someembodiments, an underfill material in liquid state is dispensed into thegap between each semiconductor die 110/112 and the interposer substrate102 to reinforce the strength of the conductive joints and therefore theoverall package structure. After the dispensing, the underfill materialis cured to form the underfill element 114.

In some embodiments, the underfill element 114 fills the whole gapbetween each semiconductor die 110/112 and the interposer substrate 102,as shown in FIG. 1B. Also, a portion of the underfill element 114 is inthe gaps between adjacent semiconductor dies 110 and 112. The underfillelement 114 exists but is not shown in FIG. 2.

As shown in FIG. 1C, an encapsulant layer 116 is further formed over theinterposer substrate 102 to surround and protect the semiconductor dies110 and 112 and the underfill element 114. The encapsulant layer 116 maybe separated from the conductive joints below the semiconductor dies 110and 112 by the underfill element 114. In some embodiments, theencapsulant layer 116 is made of or includes an insulating material suchas a molding material. The molding material may include a polymermaterial, such as an epoxy-based resin with fillers dispersed therein.In some embodiments, a molding material (such as a liquid moldingmaterial) is dispensed over the interposer substrate 102 and/or over thesemiconductor dies 110 and 112. In some embodiments, a thermal processis then used to cure the liquid molding material and to transform itinto the encapsulant layer 116.

In some embodiments, a planarization process (not shown) is also appliedon the encapsulant layer 116 to partially remove the encapsulant layer116, until the backside (e.g., the top surface 110A shown in FIG. 1C) ofeach (first) semiconductor die 110 and the backside (e.g., the topsurface 112A shown in FIG. 1C) of each (second) semiconductor die 112are exposed through the top surface 116A of the encapsulant layer 116.This facilitates the dissipation of heat generated from thesemiconductor dies 110 and 112 during operation. The planarizationprocess may include a grinding process, a chemical mechanical polishing(CMP) process, an etching process, a dry polishing process, one or moreother applicable processes, or a combination thereof. The encapsulantlayer 116 exists but is not shown in FIG. 2.

Afterwards, the carrier substrate 100 is removed to expose a secondsurface 102B (e.g., the shown lower surface) of the interposer substrate102, as shown in FIG. 1C, in accordance with some embodiments. Althoughnot shown, the remaining structure may be turned upside down and placedso that the semiconductor die side is affixed to a dicing tape (notshown). A singulation process (also referred to as a saw process) isthen performed along cutting grooves C shown in FIG. 1C, to formmultiple separate package structures, in accordance with someembodiments. In FIG. 1C, one of the package structures is shown, whichincludes an interposer substrate 102 with semiconductor dies 110 and112, an underfill element 114 and an encapsulant layer 116 thereon.Afterwards, each package structure may be removed from the dicing tape(not shown) using, for example, a pick-and-place tool (not shown).

As shown in FIG. 1D, the resulting package structure (hereinafter alsoreferred to as a semiconductor device) in FIG. 1C is disposed (by apick-and-place tool, for example) over a package substrate 120 placed onanother carrier substrate 200 (similar to the carrier substrate 100mentioned above) with the second surface 102B (e.g., the shown lowersurface) of the interposer substrate 102 facing a first surface 120A(e.g., the shown upper surface) of the package substrate 120, inaccordance with some embodiments. The package substrate 120 is used toprovide electrical connection between semiconductor devices orcomponents packaged in the package structure and an external electronicdevice, after the carrier substrate 200 is removed at a subsequent stage(illustrated in FIG. 1H) which will be further described later.

In some embodiments, after stacking the interposer substrate 102 overthe package substrate 120, it is bonded to the package substrate 120through flip-chip bonding by way of conductive elements 121 (such asconductive pillars) formed on the second surface 102B of the interposersubstrate 102 at the exposed contact pads (not shown) and conductivestructures 122 (such as micro bumps each including a metal pillar 122Aand a metal cap layer 122B over the metal pillar 122A) formed on thefirst surface 120A of the package substrate 120 at the exposed contactpads (not shown) to form conductive joints, as shown in FIG. 1D. Thebonding between the interposer substrate 102 and the package substrate120 may be solder bonding or direct metal-to-metal (such as acopper-to-copper) bonding. In some embodiments, the interposer substrate102 is bonded to the package substrate 120 through a reflow process, aspreviously discussed. The materials and formation method of theconductive elements 121 and the conductive structures 122 may be thesame or similar to those of the conductive elements 107 and theconductive structures 108, respectively, illustrated in FIG. 1B, and arenot repeated here.

The conductive joints (i.e., conductive elements 121 and the conductivestructures 122) enable electrical connection between the interposersubstrate 102 (as well as devices thereon) and the package substrate120. In some embodiments, an underfill element 118 is formed over thepackage substrate 120 to surround and protect the conductive joints, andenhances the connection between the interposer substrate 102 and thepackage substrate 120, as shown in FIG. 1D. The materials and formationmethod of the underfill element 118 may be the same or similar to thoseof the underfill element 114 illustrated in FIG. 1B, and are notrepeated here. The underfill element 118 exists but is not shown in FIG.2.

As shown in FIG. 1E, a ring structure 130 is mounted on the packagesubstrate 120, in accordance with some embodiments. The ring structure130 may be placed over the package substrate 120 using, for example, apick-and-place tool. The ring structure 130 may have a rigidity greaterthan that of the package substrate 120, and is configured as a stiffenerring for constraining the package substrate 120 to alleviate its warpageand/or to enhance robustness of the package substrate 120.

The ring structure 130 may have a substantially rectangular or squarering shape in the top view (see FIG. 2), depending on the shape of thepackage substrate 120. In some embodiments, the ring structure 130 isarranged along the periphery 120C of the package substrate 120, and agap is formed between the inner edge of the ring structure 130 and theperiphery of the interposer substrate 102. In some embodiments, the ringstructure 130 is arranged to surround the interposer substrate 102 andthe semiconductor dies 110 and 112 thereon. The ring structure 130 isbasically a flat structure, and may have a bottom surface 130A facingthe first surface 120A of the package substrate 120 and a top surface130B opposite the bottom surface 130A.

The material of the ring structure 130 may include metal such as Cu,stainless steel, stainless steel/Ni, or the like, but is not limitedthereto. In some embodiments, the material of the ring structure 130 isselected so that the coefficient of thermal expansion (CTE) of the ringstructure 130 is similar to that of the package substrate 120 to reduceCTE mismatch therebetween, thereby reducing stress (as well asdeformation) on the package substrate 120 caused by the ring structure130.

In some embodiments, the ring structure 130 is attached to the firstsurface 120A of the package substrate 120 using a non-conductiveadhesive layer 132. The adhesive layer 132 may be any suitable adhesive,epoxy, die attach film (DAF), or the like. The adhesive layer 132 may beapplied to the bottom surface 130A of the ring structure 130 or may beapplied over the first surface 120A of the package substrate 120, beforethe installation of the ring structure 130, in accordance with someembodiments.

The following will describe the installation of the thermal managementfeature of the package structure in conjunction with FIGS. 1F-1G andFIGS. 3A-3B. FIGS. 3A and 3B are respectively a cross-sectional view andan exploded view of a portion (i.e., the thermal management feature,which includes a heat dissipating lid structure, a heat sink, andvarious thermal interface material (TIM) layers) of a semiconductor diepackage in accordance with some embodiments.

As shown in FIG. 1F, a lid structure 150 is mounted on the ringstructure 130 and extends over the semiconductor dies 110 and 112, inaccordance with some embodiments. The lid structure 150 may be placedover the ring structure 130 and the semiconductor dies 110 and 112using, for example, a pick-and-place tool. The lid structure 150 mayhave a high thermal conductivity (Tk), for example, between about 200W/m·K to about 400 W/m·K or more, and may be configured as a heatspreader for dispersing heat generated from devices in the packagestructure.

The lid structure 150 may have a substantially rectangular or squareshape depending on the shape of the package substrate 120. In someembodiments, the lid structure 150 is a planar structure and hassurfaces 150A and 150B opposite to each other. The (bottom) surface 150Afaces the ring structure 130 and the semiconductor dies 110 and 112. Insome embodiments, the lid structure 150 further has openings 152penetrating the surfaces 150A and 150B. After the installation of thelid structure 150, the openings 152 are aligned with the secondsemiconductor dies 112, respectively, as shown in FIG. 1F. The openings152 may be formed by mechanical drilling (such as laser drilling) orother suitable processes. The function of the openings 152 exposing thesecond semiconductor dies 112 will be described later.

The lid structure 150 may be formed using a metal, a metal alloy, or thelike. For example, the material of lid structure 150 may include metalsand/or metal alloys such as Al, Cu, Ni, Co, the like, or a combinationthereof. In some embodiments, the lid structure 150 is formed ofsubstantially similar materials as the ring structure 130, but thedisclosure is not limited thereto.

In some embodiments, as shown in FIG. 1F, the lid structure 150 isattached to the top surface 130B of the ring structure 130 using anadhesive layer 132′ (similar to the adhesive layer 132 mentioned above),and is attached to top surface 110A of the first semiconductor die 110using a thermal interface material (TIM) layer 140. The adhesive layer132′ may be arranged along the top surface 130B of the ring structure130, in accordance with some embodiments. The adhesive layer 132′ may beapplied to the top surface 130B of the ring structure 130 or may beapplied over the bottom surface 150A of the lid structure 150, and theTIM layer 140 may be applied to the top surface 110A of the firstsemiconductor die 110 or may be applied over the bottom surface 150A ofthe lid structure 150, before the installation of the lid structure 150,in accordance with some embodiments.

The adhesive layer 132′ may have a better adhering ability and a lowerthermal conductivity than the TIM layer 140. For example, the adhesivelayer 132′ may have a thermal conductivity lower than about 0.5 W/m·K,and the TIM layer 140 may have a thermal conductivity higher than about50 W/m·K. The TIM layer 140 with better thermal conductivity helps heatdissipation of the high-power consuming semiconductor die 110. In someembodiments, the TIM layer 140 may be made of or include a high thermalconductivity material such as a metallic-based material or asolder-based material comprising Cu, Ag, indium paste, or the like.

The TIM layer 140 may be a discontinuous structure, and has openings 142for exposing the second semiconductor dies 112, as shown in FIG. 1F andFIG. 3B, in accordance with some embodiments. In some embodiments, theTIM layer 140 is formed over the semiconductor dies 110 and 112 and theencapsulant layer 116 as shown in FIG. 1F, and the openings 142 arealigned with the respective second semiconductor dies 112 to expose thesecond semiconductor dies 112. In the top view, each opening 142 maysurround the corresponding second semiconductor die 112. The positionsof openings 142 may correspond to the positions of openings 152 of thelid structure 150. In some embodiments, the openings 142 and 152 mayhave corresponding cross-sectional shapes, such as square orrectangular, depending on the shape of the second semiconductor dies112, and corresponding cross-sectional areas, as shown in FIG. 1F andFIG. 3B, but the disclosure is not limited thereto.

In some alternative embodiments, the TIM layer 140 may be a continuousstructure (i.e., no openings formed therein), and is dispensed only overthe first semiconductor die 110 and does not extend over the secondsemiconductor dies 112 and the encapsulant layer 116. For example, insome embodiments shown in FIG. 1F-1, the TIM layer 140 has the shape andsize (i.e., cross-sectional area) corresponding to the firstsemiconductor die 110, and does not cover (i.e., extend over) the secondsemiconductor dies 112 and the encapsulant layer 116 when it is arrangedabove the first semiconductor die 110.

While not shown in the cross-section of FIG. 1F (or FIG. 1F-1), itshould be understood that various interfacial layers may be presentbetween the first semiconductor die 110 and the TIM layer 140, betweenthe lid structure 150 and the TIM layer 140, as well as possibly coatinglayers on the TIM layer 140. For example, referring to FIG. 4, which isa closed-up cross-sectional view of a thermal stack in accordance withsome embodiments. As shown in FIG. 4, there is a metallization layer 115additionally formed on the backside (i.e. the upper surface 110A) of thefirst semiconductor die 110. In some embodiments, the (backside)metallization layer 115 is Ni—Cu layer, and may be co-deposited on thefirst semiconductor die 110 backside using, for example, a physicalvapor deposition (PVD) (this step is also known in the art as the“backside metallization (BSM)” process), although other suitablemetallic materials and processes may also be used in differentembodiments

In turn, the TIM layer 140, which may be In—Sn layer or In—Sn—Cu layerin some embodiments, may be applied over the metallization layer 115using, for example, a PVD process or the like. One skilled in the artwould appreciate that the TIM layer 140 may use other suitable metallicmaterials and/or may further have metallic coatings formed thereon indifferent embodiments. Through the (backside) metallization layer 115(interposed between and in contact with the first semiconductor die 110and the TIM layer 140), the TIM layer 140 establishes a metallurgicalbond with the first semiconductor die 110. For example, the abovematerials of components may combine to form a combination of materialshaving an inter-metallic structure, i.e., inter-metallic compound (IMC)layers. Such an inter-metallic structure has high thermal conductivity,and thus helps to dissipate heat generated from the high-power consumingsemiconductor die 110.

In turn, the lid structure 150, which may be made of or include Cu(although other suitable metallic material may also be used, asmentioned above), may be adapted to the TIM layer 140. It should benoted that the lid structure 150 may also have a plating layer 155 onits bottom surface 150A, and the plating layer 155 may be Ni—Cu layer insome embodiments, although other suitable metallic materials may be usedin different embodiments. In this way, an inter-metallic structure mayalso be formed between the lid structure 150 and the TIM layer 140,thereby helping to dissipate heat generated from the high-powerconsuming semiconductor die 110.

The formed thermal stack shown in FIG. 4 may be realized by performing abonding process. Such a bonding process may be performed in anoxygen-free environment such as a nitrogen (N₂) environment. The bondingprocess may occur between approximately 150 degree Celsius (□) and 210□, for a time period between several minutes to approximately 1 hour.

Next, referring to FIG. 1G, which shows a heat sink 160 (sometimes alsocalled a heat spreader) being arranged above the lid structure 150 toincrease heat dissipation, in accordance with some embodiments. The heatsink 160 may be placed over the lid structure 150 using, for example, apick-and-place tool. The heat sink 160 may also have a high thermalconductivity, for example, between about 200 W/m·K to about 400 W/m·K ormore, and may be formed of substantially similar materials as the lidstructure 150 (but the disclosure is not limited thereto). In someembodiments, the heat sink 160 further includes a cooling structureformed on the top thereof, such as cooling fins 163 (see FIGS. 3A-3B).

As shown in FIGS. 1G, 3A, and 3B, the heat sink 160 has a bottom surface160A and multiple protrusions 162 (the number of the protrusions 162 maybe determined by the number of the second semiconductor dies 112)extending from the bottom surface 160A, in accordance with someembodiments. After being installed on the lid structure 150, the bottomsurface 160A of the heat sink 160 is located over and faces the (top)surface 150B of the lid structure 150, and the protrusions 162 of theheat sink 160 can extend into the openings 152 of the lid structure 150(and the openings 142 of the TIM layer 140, if they exist). The openings152 of the lid structure 150 and/or the openings 142 of the TIM layer140 are configured to allow the protrusions 162 of the heat sink 160 topass through. In some embodiments, the protrusions 162 has thecross-sectional shape (e.g., square or rectangular) corresponding to thecross-sectional shape (e.g., square or rectangular) of the openings 152and/or the openings 142, as shown in FIG. 3B, but the disclosure is notlimited thereto.

As shown in FIG. 1G, the bottom surface 160A of the main portion (orbase portion) 161 of the heat sink 160 is attached to the top surface150B of the lid structure 150 using a TIM layer 170, in accordance withsome embodiments. Accordingly, the heat generated from the firstsemiconductor die 110 can be dissipated through a heat path (from theTIM layer 140 to the lid structure 150, to the TIM layer 170, and to theheat sink 160) indicated by the arrow P₁.

The TIM layer 170 may have a good thermal conductivity (Tk), which maybe between about 3 W/m·K to about 5 W/m·K. In some embodiments, the TIMlayer 170 is made of or include a polymer with thermal conductivefillers. Applicable thermal conductive fillers materials may includealuminum oxide, boron nitride, aluminum nitride, aluminum, copper,silver, the like, or a combination thereof. In some embodiments, the TIMlayer 170 utilizes a gel or film type polymer TIM. The TIM layer 170 maybe applied to the bottom surface 160A of the heat sink 160 (mainportion) or may be applied over the (top) surface 150B of the lidstructure 150, before the installation of the heat sink 160, inaccordance with some embodiments.

In some embodiments, the TIM layer 170 further has openings 172 (seeFIG. 3B) through which the protrusions 162 of the heat sink 160 canextend into the openings 152 (see FIG. 1F) of the lid structure 150. Theopenings 172 may be aligned with the openings 152 of the lid structure150 (and the openings 142 of the TIM layer 140, if they exist). In someembodiments, the cross-sectional shape (e.g., square or rectangular) ofthe openings 172 corresponds to the cross-sectional shape (e.g., squareor rectangular) of openings 152 (and the openings 142, if they exist),as shown in FIG. 3B, but the disclosure is not limited thereto.

After the installation of the heat sink 160, the bottom surface 162A ofthe protrusions 162 and the bottom surface 150A of the lid structure 150may be substantially at the same height as shown in FIG. 1G and FIG. 3A,but the disclosure is not limited thereto. In some alternativeembodiments, the bottom surface 162A of the protrusions 162 may also belower than (i.e., extends beyond) the bottom surface 150A of the lidstructure 150, as shown in FIG. 1H-1. Thus, the thickness T₁ of eachprotrusion 162 (i.e., the distance from the bottom surface 160A of theheat sink to the bottom surface 162A of the protrusion 162) in thevertical direction Z may be equal to or greater than the combinedthickness T₂ of the TIM layer 170 and the lid structure 150 (i.e., thedistance from the upper surface 170A of the TIM layer 170A to the bottomsurface 150A of the lid structure 150) in the vertical direction Z, invarious embodiments.

As shown in FIG. 1G, the bottom surface 162A of each protrusion 162 isattached to the top surface 112A of the corresponding secondsemiconductor die 112 using a TIM layer 180. Accordingly, the heatgenerated from the second semiconductor die(s) 112 can be dissipatedthrough another heat path (from the TIM layer 180 to the heat sink 160)indicated by the arrow P₂. As the heat path P₂ does not pass through anumber of interfaces (like the interfaces between the lid structure 150and the TIM layers 140 and 170), it reduces the contact thermalresistance from layer to layer. As a result, the heat transfer of thesecond semiconductor dies 112, as well as the thermal performance of theentire package structure, can be improved.

In some embodiments, the TIM layer 180 may have a good thermalconductivity (Tk), which may be between about 3 W/m·K to about 5 W/m·K,and may use the same or similar polymer material as the TIM layer 170.In some embodiments, the TIM layer 180 utilizes a gel or film typepolymer TIM. The TIM layer 180 may be applied to the top surface 112A ofthe corresponding second semiconductor die 112 or may be applied overthe bottom surface 162A of the corresponding protrusion 162, before theinstallation of the heat sink 160, in accordance with some embodiments.

It should be understood that because each second semiconductor die 112(low-power consuming die) generates a relative small amount of heat,compared to the first semiconductor die 110 (high-power consuming die),the TIM layer 180 having a thermal conductivity lower than that of theTIM layer 140 (in contact with the first semiconductor die 110) canstill effectively dissipate heat from the second semiconductor die 112.In addition, the TIM layer 180 using polymer TIM (instead ofmetallic-based or solder-based TIM) can not only reduce the quantity ofthe TIM layer 140 (e.g., solder TIM, which is more expensive) but alsosave (i.e., omit) the backside metallization (BSM) process performed onthe second semiconductor die 112, thereby reducing cost. Furthermore,because polymer TIM (whether it is a gel or film type film) typicallyhas a better adhering ability than metallic-based or solder-based TIM,it also reduces the risk of TIM delamination (e.g., caused by substratewarpage) during thermal cycling.

In some embodiments where the TIM layer 140 has openings 142 to exposethe second semiconductor dies 112, the TIM layers 180 are located withinthe openings 142 and in contact with the second semiconductor dies 112,as shown in FIG. 1G and FIG. 3B. The openings 142 of the TIM layer 140may surround the TIM layers 180. In some embodiments, the TIM layers 180are spaced apart from the TIM layer 140 (see FIG. 1G, for example) so asreduce thermal crosstalk between the semiconductor dies 110 and 112.

In some embodiments, the thickness T₄ of the TIM layers 180 in thevertical direction Z may be equal to or less than the thickness T₃ ofthe TIM layer 140 in the vertical direction Z, as shown in FIG. 1G andFIG. 1H-1. Note that because the TIM layer 180 has a relatively lowthermal conductivity, it should have a small thickness to increase heattransfer. In some embodiments, the thickness T₅ (see FIG. 3B) of eachcooling fin 163 of the heat sink 160 is large enough to increase heatdissipation, for example, may be larger than the combined thickness ofthe TIM layer 170, the lid structure 150, and the TIM layer 140 (or TIMlayer 180) (i.e., T₅>T₂+T₄ or T₅>T₄+T₃).

In some embodiments, the cross-sectional area of each TIM layer 180corresponds to (e.g., equal to) the cross-sectional area of the bottomsurface 162A of the corresponding protrusion 162 of the heat sink 160.For example, the TIM layer 180 may cover substantially the entire bottomsurface 162A of the corresponding protrusion 162. Also, thecross-sectional area of the bottom surface 162A of the each protrusion162 is equal to or greater than the cross-sectional area of the uppersurface 112A of the corresponding second semiconductor die 112, inaccordance with some embodiments. For example, each second semiconductordie 112 has a width W₁ and a length L₁ in cross section (see FIG. 2),and the bottom surface 162A of the each protrusion 162 has a width W₂and a length L₂ in cross section (see FIG. 3B). The width W₂ may beequal to or greater than the width W₁, and the length L₂ may be equal toor greater than length L₁. This (large contact area) helps thesemiconductor dies 112 to quickly dissipate heat.

Many variations and/or modifications can be made to embodiments of thedisclosure. For example, although in the above embodiments theprotrusions 162 of the heat sink 160 (as well as the TIM layers 180) andthe second semiconductor dies 112 are in a one-to-one configuration, thedisclosure is not limited thereto.

FIGS. 5A and 5B are respectively a cross-sectional view and an explodedview of a portion (the thermal management feature as discussed above) ofanother semiconductor die package in accordance with some otherembodiments. In the embodiments of FIGS. 5A-5B, each protrusion 162 ofthe heat sink 160 (and each TIM layer 180) is configured to correspondto two second semiconductor dies 112 (see FIG. 2) on one side of thefirst semiconductor die 110 and arranged in a linear direction (e.g.,the direction Y shown in FIG. 2). The length of each protrusion 162 (andeach TIM layer 180) in the direction Y may be equal to or greater thanthe combined length of the corresponding two second semiconductor dies112 in the direction Y so as to improve heat dissipation. Also, theconfiguration of the openings of TIM layer 170, lid structure 150, andTIM layer 140 are changed accordingly.

FIGS. 6A and 6B are respectively a cross-sectional view and an explodedview of a portion (the thermal management feature as discussed above) ofyet another semiconductor die package in accordance with some otherembodiments. In the embodiments of FIGS. 6A-6B, each protrusion 162 ofthe heat sink 160 (and each TIM layer 180) is configured to correspondto four second semiconductor dies 112 (see FIG. 2) on one side of thefirst semiconductor die 110 and arranged in the direction Y. Similarly,the length of each protrusion 162 (and each TIM layer 180) in thedirection Y may be equal to or greater than the combined length of thecorresponding four second semiconductor dies 112 in the direction Y soas to improve heat dissipation. Also, the configuration of the openingsof TIM layer 170, lid structure 150, and TIM layer 140 are changedaccordingly.

One of ordinary skill in the art will appreciate that the abovearrangement examples of the thermal management feature are provided forillustrative purposes, and other suitable arrangements may also be used.

Next, referring to FIG. 1H. As shown in FIG. 1H, the carrier substrate200 (in FIG. 1G) is removed to expose a second surface 120B (e.g., theshown lower surface) of the package substrate 120, after theinstallation of the heat sink 160, in accordance with some embodiments.Conductive bumps 190 are then formed over the second surface 120B thatis originally covered by the carrier substrate 200. Each conductive bump190 may be electrically connected to one of the exposed contact pads(not shown) of the package substrate 120. The conductive bumps 190enable electrical connection between the package structure and anexternal electronic device such as a PCB (not shown). The conductivebumps 190 may be or include solder bumps such as tin-containing solderbumps. The tin-containing solder bumps may further include copper,silver, gold, aluminum, lead, one or more other suitable materials, or acombination thereof. In some embodiments, the tin-containing solder bumpis lead-free.

In some embodiments, solder balls (or solder elements) are disposed onthe exposed contact pads of the second surface 120B after the removal ofthe carrier substrate 200. A reflow process is then carried out to meltthe solder balls into the conductive bumps 190. In some otherembodiments, under bump metallization (UBM) elements are formed over theexposed contact pads before the solder balls are disposed. In some otherembodiments, solder elements are electroplated onto the exposed contactpads. Afterwards, a reflow process is used to melt the solder element toform the conductive bumps 190.

As a result, the process for forming the resulting semiconductor diepackage illustrated in FIG. 1H is completed.

FIG. 7 is a simplified flowchart illustrating a process flow 700 forforming a semiconductor die package in accordance with some embodiments.For illustration, the flowchart will be described along with thedrawings shown in FIGS. 1D-1G. Some of the described operations can bereplaced or eliminated in different embodiments. Alternatively, someoperations may be added in different embodiments.

The process flow 700 includes operation 701, in which a firstsemiconductor die (e.g., a high-power consuming die) 110 and a secondsemiconductor die (e.g., a low-power consuming die) 112 is bonded to apackage substrate 120, as illustrated in FIG. 1D. The process flow 700also includes operation 702, in which a ring structure 130 is mounted onthe package substrate 120 to surround the first and second semiconductordies 110 and 112, as illustrated in FIG. 1E. The process flow 700 alsoincludes operation 703, in which a lid structure 150 is mounted on thering structure 130 and above the first and second semiconductor dies 110and 112, as illustrated in FIG. 1F. In some alternative embodiments, thelid structure 150 and the ring structure 130 are integrally formedstructure (i.e., an one-piece structure), and such an one-piecestructure is attached to the package substrate 120 in a single stepusing the adhesive layer 132, as shown in FIG. 1F-2.

The operation 703 further includes attaching the lid structure 150 tothe first semiconductor die 110 using a first thermal interface material(TIM) layer 140 interposed between the bottom surface 150A of the lidstructure 150 and the upper surface 110A of the first semiconductor die110, as illustrated in FIG. 1F (or FIG. 1F-1 or FIG. 1F-2). In someembodiments, the material of first TIM layer 140 includes ametallic-based material or a solder-based material. In this case, theprocess flow 700 may further include an operation of providing ametallization layer 115 (see FIG. 4) on the upper surface 110A of thefirst semiconductor die 110 before forming the first TIM layer 140 onthe upper surface (i.e., backside) 110A of the first semiconductor die110. The (backside) metallization layer 115 is used to help the firstTIM layer 140 and the first semiconductor die 110 to establish ametallurgical bond (through a bonding process as described above), whichhelps to dissipate heat generated from the first semiconductor die 110.

The process flow 700 also includes operation 704, in which a heat sink160 is mounted on the lid structure 150, as illustrated in FIG. 1G. Insome embodiments, the heat sink 160 is attached to the top surface 150Bof the lid structure 150 using another TIM layer 170, which may bepolymer TIM and may have a thermal conductivity lower than that of thefirst TIM layer 140. In some embodiments, the heat sink 160 has aprotrusion 162 extending from its bottom surface 160A, and theprotrusion 162 can extend into the opening 152 of the lid structure 150after the installation of the heat sink 160. In some embodiments, thefirst TIM layer 140 may have openings 142 (see FIG. 1F and FIG. 3B)and/or the TIM layer 170 may have openings 172 (see FIG. 3B) to allowthe protrusion 162 of the heat sink 160 to pass through.

Additionally, the operation 704 further includes attaching theprotrusion 162 of the heat sink 160 to the second semiconductor die 112using a second TIM layer 180 interposed between the bottom surface 162Aof the protrusion 162 and the upper surface 112A of the secondsemiconductor die 112, as illustrated in FIG. 1G. In some embodiments,the second TIM layer 180 may also be polymer TIM and may have a thermalconductivity lower than that of the first TIM layer 140. The second TIMlayer 180 may use the same or similar material as the TIM layer 170. Insome embodiments, the second TIM layer 180 is provided on the bottomsurface 162A of the protrusion 162 or provided on the upper surface 112Aof the second semiconductor die 112, before the mounting of the heatsink (operation 705). In some embodiments, the first TIM layer 140 andthe second TIM layer 180 are provided in such a way that the second TIMlayer 180 is spaced apart from the first TIM layer 140.

As mentioned above, a semiconductor die package and the method forforming the same are provided in accordance with some embodiments of thedisclosure. In the package structure, the heat sink has protrusionsextending into the openings of the lid structure, and the heat sinkprotrusions are attached to the second semiconductor dies (low-powerconsuming dies) using TIM layers. This helps to improve the heattransfer of the second semiconductor dies by reducing the contactthermal resistance from layer to layer. In some embodiments, the TIMlayers in contact with the second semiconductor dies may utilize polymerTIM instead of expensive metallic-based or solder-based TIM, and the BSMprocess performed on the second semiconductor dies can thus be omitted,thereby reducing cost. In addition, because polymer TIM typically has abetter adhering ability than metallic-based or solder-based TIM, it alsoreduces the risk of TIM delamination during thermal cycling. As aresult, the reliability of the entire package is improved.

In accordance with some embodiments, a semiconductor die package isprovided. The semiconductor die package includes a package substrate, asemiconductor device, a ring structure, a lid structure, a heat sink, afirst thermal interface material (TIM) layer, and a second TIM layer.The package substrate has a first surface. The semiconductor device isdisposed over the first surface of the package substrate. The ringstructure is attached to the first surface of the package substrate andsurrounds the semiconductor device. The lid structure is attached to thering structure and disposed over the semiconductor device. The lidstructure also has a first opening exposing the a first part of thesemiconductor device. The heat sink is disposed over the lid structureand has a first portion and a second portion. The first portion of theheat sink is attached to the upper surface of the lid structure. Thesecond portion of the heat sink extends into the first opening of thelid structure and is attached to the upper surface of the first part ofthe semiconductor device. The first TIM layer is interposed between thebottom surface of the lid structure and the upper surface of a secondpart of the semiconductor device. The second TIM layer is interposedbetween the bottom surface of the second portion of the heat sink andthe upper surface of the first part of the semiconductor device. Thefirst TIM layer has a thermal conductivity higher than the thermalconductivity of the second TIM layer.

In accordance with some embodiments, a semiconductor die package isprovided. The semiconductor die package includes a package substrate, afirst semiconductor die, a second semiconductor die, a ring structure, alid structure, a heat sink, a first TIM layer, and a second TIM layer.The package substrate has a first surface. The first and secondsemiconductor dies are disposed over the first surface of the packagesubstrate, and the power consumption of the first semiconductor die isgreater than the power consumption of the second semiconductor die. Thering structure is attached to the first surface of the package substrateand surrounds the first and second semiconductor dies. The lid structureis attached to the ring structure and disposed over the first and secondsemiconductor dies. The lid structure also has a first opening exposingthe second semiconductor die. The heat sink is disposed over the lidstructure. The heat sink has a bottom surface facing the upper surfaceof the lid structure, and a protrusion extending from the bottom surfaceinto the first opening of the lid structure. The first TIM layer isinterposed between the bottom surface of the lid structure and the uppersurface of the first semiconductor die. The second TIM layer isinterposed between the bottom surface of the protrusion of the heat sinkand the upper surface of the second semiconductor die. The first TIMlayer has a thermal conductivity higher than the thermal conductivity ofthe second TIM layer.

In accordance with some embodiments, a method for forming asemiconductor die package is provided. The method includes bonding afirst semiconductor die and a second semiconductor die to a firstsurface of a package substrate. The method also includes mounting a ringstructure on the first surface of the package substrate to surround thefirst and second semiconductor dies. The method also includes mounting alid structure on the ring structure and above the first and secondsemiconductor dies, wherein the lid structure has a first openingexposing the second semiconductor die. The method also includesattaching the lid structure to the first semiconductor die using a firstTIM layer interposed between the bottom surface of the lid structure andthe upper surface of the first semiconductor die. The method furtherincludes mounting a heat sink on the lid structure, wherein the heatsink has a first portion located over the upper surface of the lidstructure, and a second portion extending into the first opening of thelid structure. In addition, the method includes attaching the secondportion of the heat sink to the second semiconductor die using a secondTIM layer interposed between the bottom surface of the second portion ofthe heat sink and the upper surface of the second semiconductor die. Thefirst TIM layer has a thermal conductivity higher than the thermalconductivity of the second TIM layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1-15. (canceled)
 16. A method for forming a semiconductor die package, comprising: bonding a first semiconductor die and a second semiconductor die to a first surface of a package substrate; mounting a ring structure on the first surface of the package substrate to surround the first and second semiconductor dies; mounting a lid structure on the ring structure and above the first and second semiconductor dies, wherein the lid structure has a first opening exposing the second semiconductor die; attaching the lid structure to the first semiconductor die using a first thermal interface material (TIM) layer interposed between a bottom surface of the lid structure and an upper surface of the first semiconductor die; mounting a heat sink on the lid structure, wherein the heat sink has a first portion located over an upper surface of the lid structure, and a second portion extending into the first opening of the lid structure; and attaching the second portion of the heat sink to the second semiconductor die using a second TIM layer interposed between a bottom surface of the second portion of the heat sink and an upper surface of the second semiconductor die, wherein the first TIM layer has a thermal conductivity higher than a thermal conductivity of the second TIM layer.
 17. The method as claimed in claim 16, wherein the first TIM layer comprises a metallic-based material or a solder-based material, and the second TIM layer comprises a polymer with thermal conductive fillers, and wherein the method further comprises: providing a metallization layer on the upper surface of the first semiconductor die before forming the first TIM layer on the upper surface of the first semiconductor die, wherein the metallization layer is used to help the first TIM layer and the first semiconductor die to establish a metallurgical bond.
 18. The method as claimed in claim 16, wherein the second TIM layer is formed on the bottom surface of the second portion of the heat sink before the mounting of the heat sink.
 19. The method as claimed in claim 16, further comprising: providing a third TIM layer between a bottom surface of the first portion of the heat sink and the upper surface of the lid structure, wherein the third TIM layer has a second opening to allow the second portion of the heat sink to pass through.
 20. The method as claimed in claim 16, wherein the first TIM layer and the second TIM layer are provided in such a way that the second TIM layer is spaced apart from the first TIM layer.
 21. The method as claimed in claim 16, wherein the first TIM layer is disposed over the first and second semiconductor dies and having a second opening exposing the second semiconductor die, and the second opening of the first TIM layer surrounds the second TIM layer.
 22. The method as claimed in claim 21, further comprising: providing a third TIM layer between a bottom surface of the first portion of the heat sink and the upper surface of the lid structure, wherein the third TIM layer has a third opening through which the second portion of the heat sink extends into the first opening of the lid structure.
 23. The method as claimed in claim 16, wherein a thickness of the second TIM layer in a vertical direction is equal to or less than a thickness of the first TIM layer in the vertical direction.
 24. The method as claimed in claim 16, wherein a cross-sectional area of the second TIM layer corresponds to a cross-sectional area of the bottom surface of the second portion of the heat sink, and the cross-sectional area of the bottom surface of the second portion of the heat sink is equal to or greater than a cross-sectional area of the upper surface of second semiconductor die.
 25. The method as claimed in claim 16, wherein a power consumption of the first semiconductor die is greater than a power consumption of the second semiconductor die.
 26. A method for forming a semiconductor die package, comprising: disposing a semiconductor device over a first surface of a package substrate; mounting a ring structure on the first surface of the package substrate to surround the semiconductor device; mounting a lid structure on the ring structure and above the semiconductor device, wherein the lid structure has a first opening exposing a first part of the semiconductor device; attaching the lid structure to a second part of the semiconductor device using a first thermal interface material (TIM) layer interposed between a bottom surface of the lid structure and an upper surface of the second part of the semiconductor device; mounting a heat sink on the lid structure, wherein the heat sink has a first portion located over an upper surface of the lid structure, and a second portion extending into the first opening of the lid structure; and attaching the second portion of the heat sink to the first part of the semiconductor device using a second TIM layer interposed between a bottom surface of the second portion of the heat sink and an upper surface of the first part of the semiconductor device, wherein the first TIM layer has a thermal conductivity higher than a thermal conductivity of the second TIM layer.
 27. The method as claimed in claim 26, wherein the first TIM layer comprises a metallic-based material or a solder-based material, and the method further comprises: forming a metallization layer on the upper surface of the second part of the semiconductor device disposing the first TIM layer on the upper surface of the second part of the semiconductor device, wherein the first TIM layer establishes a metallurgical bond with the second part of the semiconductor device through the metallization layer.
 28. The method as claimed in claim 26, wherein the second TIM layer comprises a polymer with thermal conductive fillers.
 29. The method as claimed in claim 26, wherein the first TIM layer is disposed over the semiconductor device and having a second opening exposing the first part of the semiconductor device, and the second opening of the first TIM layer surrounds the second TIM layer.
 30. The method as claimed in claim 29, wherein the second TIM layer is spaced apart from the first TIM layer.
 31. The method as claimed in claim 26, wherein a thickness of the second TIM layer in a vertical direction is less than a thickness of the first TIM layer in the vertical direction.
 32. The method as claimed in claim 26, wherein the semiconductor device further has a plurality of first parts arranged in a first direction, wherein the first opening of the lid extends in the first direction and exposes the plurality of first parts, and wherein the second portion of the heat sink extends in the first direction and is attached to upper surfaces of the plurality of first parts through the second TIM layer that extends in the first direction and across the first parts.
 33. A method for forming a semiconductor die package, comprising: bonding a first semiconductor die and a second semiconductor die to a first surface of a package substrate, wherein a power consumption of the first semiconductor die is greater than a power consumption of the second semiconductor die; mounting a ring structure on the first surface of the package substrate to surround the first and second semiconductor dies; mounting a lid structure on the ring structure and above the first and second semiconductor dies, wherein the lid structure has a first opening exposing the second semiconductor die, and attaching the lid structure to the first semiconductor die using a first thermal interface material (TIM) layer interposed between a bottom surface of the lid structure and an upper surface of the first semiconductor die; and mounting a heat sink on the lid structure, wherein the heat sink has a first portion located over an upper surface of the lid structure and a second portion extending into the first opening of the lid structure, and attaching the second portion of the heat sink to the second semiconductor die using a second TIM layer interposed between a bottom surface of the second portion of the heat sink and an upper surface of the second semiconductor die, wherein the first TIM layer comprises a metallic-based material or a solder-based material and the second TIM layer comprises a polymer with thermal conductive fillers, and wherein the second TIM layer is spaced apart from the first TIM layer.
 34. The method as claimed in claim 33, wherein the first TIM layer is a discontinuous structure and has a second opening exposing the second semiconductor die, and the second opening of the first TIM layer surrounds the second TIM layer.
 35. The method as claimed in claim 33, further comprising: providing a metallization layer on the upper surface of the first semiconductor die before forming the first TIM layer on the upper surface of the first semiconductor die, wherein the metallization layer is used to help the first TIM layer and the first semiconductor die to establish a metallurgical bond. 